library ieee;
use ieee.std_logic_1164.all;

entity dffrnand is
port(a,b,clk:in std_logic;
	q:out std_logic);
	
end dffrnand;


architecture bhv of dffrnand is
signal temp : std_logic;
begin

temp <= a NAND b;

process(clk)
	begin
	if (clk'event and clk='1') then
		q<=temp;
	end if;
end process;

end bhv;